1. Field of the Invention
The present invention relates in general to a metal-oxide-semiconductor field-effect transistor (MOSFET). In particular, the present invention relates to an improved MOSFET and its method of fabrication, with the MOSFET having reduced parasitic capacitance in the overlapped area of the gate and drain regions, as well as suppressed gate-induced drain-leakage (GIDL) current.
2. Technical Background
As the trend of integrated circuits miniaturization continues to push the semiconductor fabrication process deeper into submicron resolution, the direct result of this reduction in the dimension of the structural configuration is a change in the device characteristics.
For example, FIG. 1 depicts a cross-sectional view of a conventional MOSFET, which is utilized for the purpose of the description of the present invention. As seen in the drawing, in the conventional MOSFET, a gate oxide layer 10 is first formed on a P-type semiconductor substrate 1. Then, a gate electrode 12 is formed on the top of the gate oxide layer 10. A pair of N-type lightly-doped (N-) drain/source regions 100 are formed in the P-type substrate 1 on either side of the gate oxide layer 10. Another pair of N-type heavily-doped (N+) drain/source regions 102 are further formed adjacent to the N-type lightly-doped (N+) drain/source regions 100. The outer edge of the lightly-doped (N-) each drain/source region 100 is adjacent the inner edge of the neighboring heavily-doped (N+) drain/source region 102, as can be seen in FIG. 1.
The reduction in the thickness of the gate oxide layer, as a consequence of submicron fabrication processes, would lead directly to an increase of the parasitic capacitance in the overlapping region of the gate and drain regions of the MOSFET device, since the distance between the gate and drain regions is also reduced to a scale of about several hundred .ANG. (10-8 cm).
As a result of the increasing parasitic capacitance in the overlapping gate and drain regions, the maximum frequency of the MOSFET semiconductor device is restricted, thereby limiting the application of such MOSFET devices in such areas as analog common source amplifiers as well as in high speed digital.
Moreover, the reduction of the dimension of the gate oxide layer also results in an increase in the electric field intensity in the region where the gate and drain overlap. This intensified electric field increases the leakage current produced as a result of the gate-induced drain-leakage effect. As a result of the reduced thickness of the gate oxide layer, the gate induced drain leakage effect induces band-to-band tunneling and causes a leakage current to flow from the gate of the MOSFET to the depletion region in the gate and drain overlapping region.
Therefore, in the art of fabrication of MOSFET semiconductor devices, efforts have been concentrated on issues including reduction of parasitic capacitance in the gate and drain overlapping region, as well as the reduction of the electric field intensity generated in the gate and drain overlapping region.